1. The need for more complex and smaller wireless communication systems has pushed semiconductor processing technology to smaller and smaller line widths. By 2010, 45 micron line technology will be considered standard; however, there is great concern about the wafer yield given such small line widths. The wafer yield is highly dependent on the ability of the semiconductor metrology to control the processing steps during wafer etching. In turn, the accuracy of the metrology system is based on the accuracy and speed of the numerical models for light scattering from line structures on the wafer. Also, going to smaller line widths requires modeling of more complicated structures on the wafer to better control wafer etching down to submicron precision. In this project, we propose a new method to model three-dimensional periodic structures that has the capability to handle geometries with the complexity necessary to perform metrology for 45 micron technology.